1. Field of the Invention
This invention relates to integrated circuits (ICs) and, more particularly, to an internal test circuit that may be used for supplying a highly controlled amount of jitter and/or duty cycle distortion to one or more circuit components arranged upon a common printed circuit board.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Many electronic systems (such as communication systems, computer systems, etc.) communicate by transmitting digital data signals between transmitting and receiving portions of the system. To avoid errors, the system receiver must sample the received data signal at the same frequency and phase with which the signal was initially digitized by the system transmitter.
In some cases, the transmitter may send a clock signal along with the digital data signal for controlling the timing with which the receiver samples the digital data signal. In other cases, the receiver may include a clock recovery system for generating the sample clock locally. For example, the receiver may use a feedback control system to adjust the frequency and phase of the sample clock signal based on data analysis the receiver acquires by observing the data signal.
Although the transmitter may synchronize the edges (or “signal transitions”) of a digital data signal to the edges of a sample clock signal, variations in signal edge timing (i.e., “jitter”) may cause the receiver to incorrectly sample the received data signal. For example, noise introduced into the transmitter (or within the clock or data signal paths) may cause the received data signal to appear “jittery” relative to the clock signal edges. The received data signal may also appear “jittery” to a receiver employing a clock recovery system when feedback errors or noise are introduced therein.
In general, “jitter” may be defined as the cycle-to-cycle variation in the threshold crossings of a signal. In other words, jitter may occur when the edges or transitions of a signal are shifted in time by different amounts over consecutive clock cycles. The signal transitions may be shifted either forward or backward. In some cases, jitter may cause the data signal to be shifted sufficiently in time to produce a “bit error” at the receiver when the data signal is incorrectly sampled by the clock signal. The bit error rate (BER) (i.e., the percentage of bit errors relative to the total number of bits received in a transmission) may be used to indicate how often a data signal must be retransmitted due to an error. High performance systems are typically characterized by low bit error rates.
The ability of a receiver to correctly sample a data signal in the presence of jitter is known as “jitter tolerance.” In some cases, jitter tolerance may be defined as the amount of peak-to-peak jitter that can be present within a received signal without causing an unacceptable bit error rate. The measurement of jitter tolerance has become an important step in the manufacture of high-speed integrated circuits and receivers. In other words, the need to measure jitter tolerance has become increasingly more critical as timing budgets become tighter, due to increased clock speeds in computer systems and higher data rates in communications systems.
A number of conventional techniques have been used to measure jitter tolerance. In computer systems (and other systems employing digital ICs), off-chip IC testers have been used to introduce jitter into a test signal supplied to a device under test (DUT). In some cases, an IC tester (100) may include a jitter signal generator (110) for applying a known amount of jitter to a signal (e.g., CLKIN) supplied to a DUT (120), as shown in FIG. 1. The DUT may be a monolithic integrated circuit (IC) chip, for example. The output of the DUT (e.g., CLKOUT)—or, the response of the DUT to the jittered input signal (e.g., CLKJITTER)—may then be passed to a response analyzer block (130) of the IC tester for determining the jitter tolerance associated with the DUT. In some cases, the response analyzer block may determine jitter tolerance by detecting the bit error rate associated with the output signal.
The type of jitter generator used to conduct the jitter tolerance test often impacts the validity of the test results. For example, some jitter generators may apply jitter by injecting noise into the input signal supplied to the DUT. The noise may be generated by a sinusoidal, deterministic or random jitter source. Unfortunately, the amplitude of the jitter added to the input signal cannot be controlled in this approach. Such jitter generators, therefore, cannot be used to measure jitter tolerance. For example, if a data bit is considered one Unit Interval (UT), the jitter amplitude may be represented as percentage of the UI. The jitter tolerance is a measure of the jitter amplitude in UI. For example, if the jitter amplitude is 0.75 UI, the jitter tolerance is also 0.75 UI. Thus, one can't measure jitter tolerance without controlling the amplitude of the jitter.
Other jitter generators may apply jitter to a control voltage supplied to a clock recovery system included within the DUT. For example, a receiver may include a phase-locked loop (PLL) or delay locked loop (DLL) device for recovering the sample clock signal. In general, PLLs are closed-loop devices that utilize voltage-controlled oscillators (VCOs) for obtaining accurate phase and frequency alignment between two signals, typically referred to as feedback and reference signals. Though similar, a DLL device differs from a PLL device in that it uses a delay line, instead of a VCO, for obtaining accurate phase and frequency alignment between the feedback and reference signals.
FIG. 2 illustrates one embodiment of a conventional PLL device 200. As shown in FIG. 2, PLL 200 may include a phase frequency detector (PFD) 210, a charge pump (CP) 220, a loop filter 230 and a voltage controlled oscillator (VCO) 240. During operational modes, PFD 210 compares the feedback signal (FVCO) to the reference signal (FREF) and generate corrective “up” and “down” pulses in response thereto. Next, charge pump 220 compares the durations of the corrective “up” and “down” pulses and generates a control current (ICTRL), representing an error signal or phase correction signal. Loop filter 230 filters the error signal and adjusts the operating frequency of VCO 240 by supplying a control voltage (VCTRL) thereto. In some cases, one or more frequency dividers (250, 260) may be included within the reference and/or feedback paths of the PLL to modulate the frequency of the reference and feedback signals.
As noted above, a jitter generator (e.g., 110, FIG. 1) may apply jitter to a DUT by modulating the VCO control voltage (VCTRL) with noise. However, in addition to producing uncontrollable jitter amplitude, modulating the VCO control voltage in such a manner may cause the output frequency of the PLL (i.e., the sample clock frequency supplied to the DUT) to shift away from a desired operating frequency. This may invalidate jitter tolerance tests performed in systems or circuits specifically designed for operating at the desired frequency. In some cases, adding noise to the VCO control voltage may cause the PLL to lock onto the noise frequency, if the noise frequency is lower than that of the loop. This, too, would impede jitter tolerance tests by not allowing a jittered test signal to be supplied to circuit components within the DUT.
Using an off-chip IC tester to perform a jitter tolerance test provides its own set of disadvantages. For example, one may wish to perform a jitter tolerance test on one or more components of a monolithic integrated circuit (IC), or one or more IC chips arranged upon a system board (such as a printed circuit board). However, it is often difficult (if not impossible) to supply a jittered test signal to only a select number of the IC chips with an off-chip IC tester. For example, although a test multiplexer may be inserted in front of each DUT (e.g., each IC chip to be jitter tested), the additional multiplexers will consume valuable space (which may or may not be available) and introduce undesirable amounts of delay and jitter to the system during normal operation. Furthermore, use of an off-chip IC tester requires external pins or connectors to be added to the IC chip for injecting the noise into the test signal. Additional logic and routing components may also be needed to supply the jittered test signal to the internal circuitry of the IC. These additional components consume additional space and increase the amount of noise added to the clock distribution path.
Therefore, a need remains for an internal test circuit capable of providing a highly controlled amount of jitter to one or more components on a monolithic integrated circuit (IC), or one or more IC chips arranged on a printed circuit board. The internal test circuit would improve upon conventional jitter generators by providing a means for determining the jitter tolerance of any chip/system component without changing the frequency of the clock signal supplied to the component or injecting noise into the clock recovery system. The internal test circuit would also provide a dynamic injection of jitter pulses and controlled duty cycle distortions into the device under test, thereby, enabling the performance of the system to be fully characterized.